1. Field of the Invention
The present invention relates generally to a communication system for packet data transmission, and in particular, to an apparatus and method for attaching error detection information to transmission information before transmission and reception of the transmission information.
2. Description of the Related Art
An IS-2000 CDMA (Code Division Multiple Access) mobile communication system, a typical mobile communication system, supports only a voice service. However, with the development of the communication technology and at the request of users, a future mobile communication system will support a data service as well as the voice service.
A mobile communication system supporting a multimedia service including voice and data services provides the voice service to a plurality of users, using the same frequency band. Further, the mobile communication system supports the data service by TDM (Time Division Multiplexing) or TDM/CDM (Time Division Multiplexing/Code Division Multiplexing). The TDM is a technique for assigning one code within a time slot assigned to a specific user. The TDM/CDM is a technique in which a plurality of users simultaneously use one time slot. The users are identified through unique codes (e.g., orthogonal codes such as Walsh codes) assigned to the users.
The mobile communication system includes a packet data channel (PDCH) for packet data transmission and a packet data control channel (PDCCH), e.g., secondary packet data control channel (SPDCCH), for efficient transmission of packet data. Packet data is transmitted over the packet data channel. Transmission of packet data on the air is performed in a physical layer packet (PLP) unit, and a length of the physical layer packet is varied at each transmission. The packet data control channel transmits a control information sequence needed to allow a receiver to efficiently receive the packet data. A length of the control information sequence is changed according to a length of the packet data. Therefore, the receiver can determine a varying length of the packet data by estimating a length of the control information sequence. The length of the control information sequence is estimated through blind slot detection (BSD).
FIG. 1 illustrates a structure of a packet data control channel transmitter in a mobile communication system to which the present invention is applied. Referring to FIG. 1, a packet data control channel input sequence, or a control information sequence transmitted over a packet data control channel, is assumed to have 13 bits per N slots (where N=1, 2, or 4). It should be noted that the number of bits included in the control information sequence is not related to a length of the control information sequence, and not limited to 13. A length of the control information sequence transmitted over the packet data control channel depends upon a length of the packet data. For example, if the packet data is either 1-slot length, 2-slot length, 4-slot length and, or 8-slot length, then the control information sequence has a selected one of 1-slot length, 2-slot length and 4-slot length. For the packet data having a 1-slot length, a control information sequence having a 1-slot length is transmitted. For the packet data having a 2-slot length, a control information sequence having a 2-slot length is transmitted. For the packet data having a 4-slot length, a control information sequence having a 4-slot length is transmitted. For the packet data having an 8-slot length, a control information sequence having a 4-slot length is transmitted. The reason for transmitting a control information sequence having a 4-slot length even for the packet data having an 8-slot length, is to prevent a preamble length from being excessively increased.
Error detection bits are attached by an error detection bit attacher 110 to the control information sequence transmitted over the packet data control channel. The error detection bit attacher 110 attaches the error detection bits to the control information sequence so that a receiver can detect a transmission error on the control information sequence. For example, the error detection bit attacher 110 attaches 8 error detection bits to the 13-bit control information sequence and generates a 21-bit control data sequence. A CRC (Cyclic Redundancy Code) generator is a typical example of the error detection bit attacher 110. The CRC generator generates a control data sequence, or CRC information-attached control information sequence, by encoding an input control information sequence with CRC. If the number of redundancy bits generated by the CRC generator is increased, the capability of detecting a transmission error will be increased. However, the increase in number of the redundancy bits for the control information sequence will reduce power efficiency. Therefore, 8 CRC bits are generally used for the error detection bits.
A tail bit attacher 120 attaches tail bits to the control data sequence output from the error detection bit attacher 110. A convolutional encoder 130 encodes the output of the tail bit attacher 120 with a convolutional code, and outputs coded symbols. For example, the tail bit attacher 120 attaches 8 tail bits all having 0's for convolutional encoding by the convolutional encoder 130, and outputs 29-bit information. The convolutional encoder 130 convolutional-encodes a control information sequence with a 1-slot length at a coding rate 1/2, and a control information sequence with a 2-slot length and a control information sequence with a 4-slot length at a coding rate 1/4. The number of symbols in the control information sequence convolutional-encoded at the coding rate 1/4 is two times larger than the number of symbols in the control information sequence convolutional-encoded at the coding rate 1/2. A symbol repeater 140 repeatedly outputs the symbols obtained by convolutional encoding the control information sequence with the 4-slot length so that the number of symbols obtained by convolutional encoding the control information sequence with a 4-slot length is two times larger than the number of symbols obtained by convolutional encoding the control information sequence with a 2-slot length. As a result, the symbol repeater 140 outputs 58N (where N=1, 2 or 4) symbols.
A puncturer 150 punctures 10N symbols among the output symbols of the symbol repeater 140 in order to minimize performance degradation and achieve proper rate matching. Therefore, the puncturer 150 outputs 48N symbols. An interleaver 160 interleaves the output symbols of the puncturer 150. The reason for using the interleaver 150 is to reduce a burst error probability by interleaving (or permuting) the order of symbols in order to solve the burst error problem caused by convolutional encoding. A bit reverse interleaver (BRI), a kind of block interleaver, can be used for the interleaver 160. The BRI increases an interval between adjacent symbols, such that the first half of the interleaved symbol sequence is comprised of even-numbered symbols and the second half of the interleaved symbol sequence is comprised of odd-numbered symbols. A modulator 170 modulates the symbols interleaved by the interleaver 160 by QPSK (Quadrature Phase Shift Keying) modulation, and generates modulated symbols for transmission.
FIG. 2 illustrates a structure of the error detection bit attacher 110 shown in FIG. 1 according to the prior art. Illustrated in FIG. 2 is an example of a CRC generator for attaching 8 CRC bits to an input control information sequence.
Referring to FIG. 2, the error detection bit attacher 110 includes a plurality of registers 211˜218, a plurality of adders 221˜224, switches SW1˜SW3, an output adder 225, and an initial value controller 230. The initial value controller 230 initializes values of the registers 211˜218 to “1” when packet data with a length of 1, 2 and 4 slots is transmitted. In contrast, the initial value controller 230 initializes values of the registers 211˜218 to “0” when packet data with a length of 8 slots is transmitted. Since both a length of the control information sequence corresponding to the packet data with a 4-slot length and a length of the control information sequence corresponding to the packet data with an 8-slot length are equally 4 slots, the receiver cannot recognize a length of the packet data from the length of the control information sequence, although it estimates a length of the control information sequence. Therefore, when the error bit detection attacher 110 generates redundant bits (or error detection bits) for a control information sequence corresponding to the packet data with a 4-slot length and a control information sequence corresponding to the packet data with an 8-slot length, the initial value controller 230 sets initial values of the registers 211˜218 to different values as stated above, so that the receiver can recognize through decoding whether the packet data with a 4-slot length and the packet data with an 8-slot length have been transmitted. After the values of the registers 211˜218 are initialized, a binary operation is performed by the output adder 225 between each bit of the input control information sequence and a value obtained by right-shifting the values of the registers 211˜218, and the operation result value is provided as an output control data sequence. During this operation, the switches SW1˜SW3 are all switched to their upper terminals. After the above operation is performed on all bits of the 13-bit control information sequence, the switches SW1˜SW3 are switched to their lower terminals, so the switches SW1 and SW2 are provided with a value “0.” Thereafter, 8 redundant bits are attached by shifting register values as many times as the number, 8, of the redundant bit.
FIG. 3 illustrates a structure of a packet data control channel receiver according to the prior art, and FIG. 4 illustrates lengths and positions of slots used when detecting a control information sequence by the receiver of FIG. 3. In particular, FIG. 3 illustrates a structure of a receiver for detecting a length of packet data by detecting a control information sequence transmitted over a packet data control channel by BSD (Blind Slot Detection). The receiver corresponds to the packet data control channel transmitter in which a CRC generator is used as an error detection bit attacher. The receiver includes CRC checkers corresponding to the CRC generator in the transmitter.
Referring to FIG. 3, the receiver includes 4 reception processing blocks 310˜340 for detecting a length of packet data. The reception processing block 310 is a block for processing a control information sequence with a 1-slot length corresponding to packet data with a 1-slot length, the reception processing block 320 is a block for processing a control information sequence with a 2-slot length corresponding to packet data with a 2-slot length, the reception processing block 330 is a block for processing a control information sequence with a 4-slot length corresponding to packet data with a 4-slot length, and the reception processing block 340 is a block for processing a control information sequence with a 4-slot length corresponding to packet data with an 8-slot length.
In the reception processing blocks 310˜340, deinterleavers 312, 322, 332 and 342 perform deinterleaving as much as the corresponding slot lengths, and depuncturers 314, 324, 334 and 344 perform depuncturing according to the corresponding slot lengths. In the reception processing blocks 330 and 340 for the control information sequence with the 4-slot length, symbol combiners 335 and 345 perform symbol combining on 2 adjacent symbols, which is a reverse operation of the symbol repetition performed by the symbol repeater 140 of FIG. 1. After the depuncturing is performed in the reception processing blocks 310 and 320 and the symbol combining is performed in the reception processing blocks 330 and 340, convolutional decoders 316, 326, 336 and 346 in the reception processing blocks 310˜340 perform convolutional decoding. The convolutional decoder 316 for the control information sequence with the 1-slot length convolutional-decodes an output of the depuncturer 314 at a coding rate 1/2. The convolutional decoder 326 for the control information sequence with the 2-slot length convolutional-decodes an output of the depuncturer 324 at a coding rate 1/4. Likewise, the convolutional decoders 336 and 346 for the control information sequence with the 4-slot length convolutional-decode outputs of the symbol combiners 335 and 345 at a coding rate 1/4, respectively. In final stages of the reception processing blocks 310˜340, CRC checkers 318, 328, 338 and 348 are arranged. The CRC checkers 318, 328, 338 and 348 perform CRC checking on the symbols convolutional-decoded by the convolutional decoders 316, 326, 336 and 346, respectively. By the CRC checking by the CRC checkers 318, 328, 338 and 348, it is determined whether a CRC error exists in the control information sequence transmitted from the transmitter. During the CRC checking, the CRC checkers 318, 328, 338 and 348 use the initial values “1” or “0” previously determined as described in conjunction with FIG. 2. That is, the CRC checker 318 detects a CRC error by setting an initial value of a decoder register to “1, ” the CRC checker 328 detects a CRC error by setting an initial value of a decoder register to “1, ” the CRC checker 338 detects a CRC error by setting an initial value of a decoder register to “1, ” and the CRC checker 348 detects a CRC error by setting an initial value of a decoder register to “0. ” A packet length detector 350 detects a length of packet data based on the reception processing results by the reception processing blocks 310˜340. Here, the 4 reception processing blocks 310˜340 can be realized with either physically separated reception processing blocks or a single reception processing block using different reception parameters.
In the receiver of FIG. 3, as a result of CRC decoding, if three reception processing blocks have errors and one reception processing block has no error, it is judged that as much packet data as a length corresponding to the error-free reception processing block was transmitted. However, if it is reported that two or more reception processing blocks have no error or all reception processing blocks have no error, it is not possible to determine which control information sequence was transmitted, resulting in a failure to receive packet data.
The receiver that detects a control information sequence by the BSD, has the following problems in a process of detecting a 2-slot control information sequence and a 4-slot control information sequence corresponding to 4-slot packet data.
Referring to FIG. 1, a 2-slot control information sequence and a 4-slot control information sequence corresponding to 4-slot packet data have the same CRC register's register initial value, and are encoded by a convolutional code with a coding rate 1/4. Next, the 4-slot control information sequence undergoes symbol repetition, thus doubling the number of symbols, whereas the 2-slot control information sequence does not undergo symbol repetition. Thereafter, a coded symbol sequence of the 2-slot control information sequence and a coded symbol sequence of the 4-slot control information sequence undergo puncturing and interleaving.
When the 4-slot control information sequence undergoes BRI interleaving, although the 2-slot control information sequence and the 4-slot control information sequence have different puncturing patterns, a considerable part of the symbol-repeated information is separately inserted in the first two slots and the last two slots. Therefore, if the reception processing block 320 for the 2-slot control information sequence, illustrated in FIG. 3, receives the 4-slot control information sequence transmitted, it is judged that the 4-slot control information sequence was correctly received with no CRC error. For example, when the 4-slot control information sequence is transmitted, the convolutional decoder 326 in the reception processing block 320 for the 2-slot control information sequence and the convolutional decoder 336 in the reception processing block 330 for the 4-slot control information sequence generate the same number, 10000, of decoded symbols. In other words the same CRC decoding results, at 2(1) and 4(1) of CRC success are shown in a row 4(1) of SPDCCH (CRC) in Table 1 obtained by an experiment. Accordingly, it is judged during CRC decoding that there is no error. As a result, it is not possible to determine a length of the packet data.
The same problem occurs even when the 2-slot control information sequence is transmitted. When the 2-slot control information sequence is transmitted, the reception processing block 330 for the 4-slot control information sequence receives information on the 2-slot control information sequence, combined with information on 2 previous slots or noises. Since an interleaving pattern and a puncturing patter for the 2-slot control information sequence are similar to an interleaving pattern and a puncturing pattern for the 4-slot control information sequence, it is judged that there is no error, even when CRC decoding on the 2-slot control information sequence is performed by the reception processing block 330 for the 4-slot control information sequence. For example, when the 2-slot control information sequence is transmitted, the convolutional decoder 326 in the reception processing block 320 for the 2-slot control information sequence and the convolutional decoder 336 in the reception processing block 330 for the 4-slot control information sequence generate the almost same number, 10000 and 7902, of decoded symbols. That is, almost the same CRC decoding results, at 2(1) and 4(1) of CRC success in a row 2(1) of SPDCCH (CRC) are shown in Table 1. Accordingly, it is judged during CRC decoding that there is no error. As a result, it is not possible to determine a length of the packet data.
In addition, as the outputs of the convolutional decoders 326 and 336 are identical (or nearly identical) to each other, information bits of the received control information sequence, for example, information bits indicating a user to which the control information sequence was transmitted, or retransmission-relation information bits, are also equally received at the reception processing block 320 for the 2-slot control information sequence and the reception processing block 330 for the 4-slot control information sequence. Therefore, although the information bits in the control information sequence are used, it is not possible to distinguish a slot length of the control information sequence. As a result, it is not possible to determine a length of the packet data.
Such a problem is shown in Table 1. Table 1 illustrates simulation results obtained by transmitting each of control information sequences with a slot length of 1(1), 2(1), 4(1) and 4(0) 10,000 times in a noise-free state. Here, “1” and “0” in the parenthesis indicate initial values to which all registers in the CRC generator are initialized. The result values obtained through the computer simulation include a successful detection probability Pd, a false probability Pfa of recognizing an incorrect slot length as a correct slot length, a mis-probability Pm of mistaking a correct slot length for an incorrect slot length, and an error probability Pe, the sum of the false probability Pfa and the mis-probability Pm. It is noted in Table 1 that the error probability Pe in detecting a control information frame comprised of 2(1) slots and 4(1) slots is abnormally high.
TABLE 1SPDCCH(CRC)PdPfaPmPe1(1)9.881e−010.000e+001.190e−021.190e−022(1)2.081e−010.000e+007.919e−017.919e−014(1)0.000e+000.000e+001.000e+001.000e+004(0)9.963e−010.000e+003.700e−033.700e−03Dedicated toother CRC symbolsSPDCCHCRC success12(CRC)1(1)2(1)4(1)4(0)(1)(1)4(1)4(0)1(1)1000040433804043382(1)341000079025340754(1)4710000100000470004(0)37001000037000